When a manufactured integrated circuit die fails scan-based structural testing, logic diagnosis is typically used to determine the source of the failure inside the die. This information enables root cause analysis that can lead to fabrication process and/or design changes that result in an overall higher yield. Logic diagnosis tools today can determine the most likely location inside a failing die from which the failures originate. However, this location information (which is typically a pin or a net in the design) does not tell whether the real defect is a defect on the interconnecting wire (also called a back end defect) or a defect inside the library cell (also called a cell internal defect or front end defect) associated with the identified location.
With integrated circuit fabrication technology advancing from 90 nm to 65 nm and beyond, the ability to distinguish between a cell internal defect and an interconnect defect is becoming critical for faster defect localization. The main reason for this is that, for 90 nm and beyond, a significant number of manufacturing defects and systematic yield limiters lie inside library cells. One of the causes of this is the increasing use of custom designed cells to cope with higher process variations. Hence, for failed dies, it is important to know whether the defect lies inside a cell or on an interconnecting wire. This leads to a faster and cheaper physical failure analysis (PFA) process because the failing die can be directly de-layered all the way down to metal layer 1 (where all the intra-cell connections are) without the need to look at metal layer 2 or higher. This speed-up is becoming more significant with shrinking fabrication technologies that use more and more metal layers. Having fewer layers to examine during PFA also reduces the overall cost of the process. Finally, knowing cell internal defects greatly helps in collecting defect statistics that can point to systematic yield limiting issues in library cells. As an example, for a low yielding wafer, if the majority of the defects are in cells then this can point to certain process steps without going through PFA.
Previous work on cell internal diagnosis can be put in two general categories. Conventional diagnosis works on a logic level model of the design, which may not preserve the actual physical implementation of library cells. Hence, the first category of techniques uses an enhanced model of the design to perform a diagnosis. These techniques can be referred to as defect model-based diagnosis techniques. The models preserve enough physical level information to represent a class of defects inside a cell e.g. transistor level bridges, or transistor stuck opens etc. Doing so enables the diagnosis to identify defects inside a cell. Another variant of such a technique uses a pattern fault model, which models specific defect behaviour by pre-specifying conditions under which a defect may be excited. These conditions can be determined by simulating likely defect types. The main drawback of such techniques is the dependence on a specific defect model for diagnosis. This is risky since unknown defect types, not represented in the model, may go undiagnosed.
A second category of techniques, referred to as excitation condition-based diagnosis, does not require any special circuit model. It is based on the realistic assumption that the excitation of a defect inside a cell will be highly correlated to the logic values at the input pins of the cell. On the other hand, the behaviour of an interconnect defect (e.g. a bridge) will depend more on the logic values on the nets neighbouring a defective wire. Based on this assumption, failing patterns (test patterns that fail on the automatic test equipment (ATE) for a failing die) are used to determine input logic value combinations that potentially excite a cell internal defect, also referred to as failing excitation conditions, for selected candidate cells. Similarly, observable passing patterns (test patterns that pass on the ATE for the failing die but are capable of observing a fault effect at the defect site) are used to determine passing excitation conditions (conditions that do not excite or propagate the defect inside the cell) for candidate cells. Based on the assumption above, a defective cell can be isolated from interconnect defects by correlating the passing and failing conditions. Furthermore, the excitation conditions determined in this process can be used along with SPICE or switch level simulations to determine the actual defect inside the cell.
Considering the advantages of the excitation condition-based diagnosis, this technique was tested in a controlled experiment in which cell internal defects were injected and corresponding fail logs were generated by simulation for an industrial design. These fail logs were then diagnosed using the excitation condition-based strategy. Surprisingly, the technique was able to correctly identify the defective cell in only 25% of the cases. Therefore, there is a need for an improved excitation condition-based diagnosis in order to detect faults in library cells or on interconnects.